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Venkatesh, C.
- A Trivial Scheme for Detecting and Preventing Unauthorized Access of Resources on a Network Domain
Authors
1 Anna University of Technology, Coimbatore, Tamilnadu, IN
2 EBET Group of Institutions, Kankayam, Tamilnadu, IN
Source
Networking and Communication Engineering, Vol 3, No 2 (2011), Pagination: 132-135Abstract
The significant success and growth of Internet is that any application can send anything to any one any time, without needing to obtain advance permission from network administrators. This openness of the internet architecture leads to unauthorized access. Defending against these types of illicit access is the hardest security problems on the internet. To solve this problem, the proposed light weight scheme to detect and prevent the unauthorized request, instead of being able to send anything to anyone at the time, the sender must obtain the endorsement secret key or secret code from the destination server. To validate the legitimate of the request, a network Authentication Server (AS) performs an authentication process for each initiating host. The simulation result proves its effectiveness for preventing unauthorized access on network resource.Keywords
IP Spoofing, Key Distribution, Authentication Process.- Fuzzy-Neuro Logic in Segmentation of MRI Images
Authors
1 Department of ECE, AITS, Rajampet, Andhra Pradesh, IN
2 AITS, Rajampet, Andhra Pradesh, IN
Source
Fuzzy Systems, Vol 4, No 3 (2012), Pagination: 103-107Abstract
Image segmentation is an important process to extract information from complex medical images. Segmentation has wide application in medical field. The main objective of image segmentation is to partition an image into mutually exclusive and exhausted regions such that each region of interest is spatially contiguous and the pixels within the region are homogeneous with respect to a predefined criterion. Widely used homogeneity criteria include values of intensity, texture, color, range, surface normal and surface curvatures. During the past, many researchers in the field of medical imaging and soft computing have made significant survey in the field of image segmentation. Several diagnostics are based proper segmentation of the digitized image. Segmentation of medical images is needed for applications involving estimation of the boundary of an object, classification of tissue abnormalities, shape analysis, contour detection. In particular Fuzzy-Neuro logic segmentation algorithm is used to provide satisfactory results compared to K-means, Fuzzy C-Means, Neural Network and Fuzzy logic. This paper aims to develop an improved method of segmentation using Fuzzy-Neuro logic to detect various tissues like white matter, gray matter; cerebral spinal fluid and tumor for a given magnetic resonance image data set. In particular Fuzzy-Neuro logic segmentation algorithm is used to provide satisfactory results compared to K-means, Fuzzy C-Means, Neural Network and Fuzzy logic.Keywords
Fuzzy-Neuro Logic, Segmentation, Neural Network, K-Means, Fuzzy C-Means.- FPGA Implementation of Digit-Serial Architecture for Various Digit-Size and Wordlength in Viterbi Decoder
Authors
1 Electronic and Instrumentation Department, Kongu Engineering College, Tamil Nadu, IN
2 Electrical Engineering Department, Kongu Engineering College, Tamil Nadu, IN
3 EBET Group of Institutions, Tamil Nadu, IN
Source
Digital Signal Processing, Vol 4, No 7 (2012), Pagination: 315-320Abstract
Convolutional code is an essential Forward Error Correcting (FEC) code for many wireless communication systems. Viterbi decoder is an optimal algorithm for decoding a convolution code. The design of an efficient Integrated Circuit (IC) in terms of power, area and speed simultaneously has become a challenging problem. Power dissipation is recognized as a critical parameter in modern Very Large Scale Integrated circuit (VLSI) design field. The major source of power dissipation is dynamic power dissipation, which is due to the total switching activity. Viterbi decoder employed in digital wireless communication is complex and dissipates large power. The proposed method focuses on power reduction of Viterbi decoderat architecture level. The proposed method is to obtain high speed and low power Viterbi decoder using digit-serial architecture for various digit size and word length. In the digit-serial architecture N bits are processed per clock cycle and a word is processed per W/N clock cycles (W-word length, N-digit size). Digit-serial architecture achieves high speed and low power. Viterbi decoder is designed with code rate k/n=¼, constraint length K= 3, word length W=8, 32 and digit size N=2, 4. The functionality is simulated and verified using Modelsim and synthesized using Xilinx FPGA SPARTAN3.Keywords
Digit-Serial Architecture, Digit-Size, Unfolding.- An Online Embedded Handheld Writing System by Finger Writing in the Air
Authors
1 Department of ECE, AITS, Rajampet - 516126, Andhra Pradesh, IN
Source
Indian Journal of Science and Technology, Vol 9, No 43 (2016), Pagination:Abstract
Objective/Background: Nowadays many writing systems are operated with physical touch of human fingers. The main objective of this paper is to transmit data by writing in the air using human figure. Methods/Statistical Analysis: In this work a novel method is proposed, based on the finger tip movements (gestures) captured by camera, using open CV math libraries the system translates the threshold image into time-series acceleration signals and feature vectors which recognizes characters or digits written in the air. Findings: Based on the color transformation the data is displayed in any of RGB colors on LCD display and displayed data transmits to the Mobile or Laptop through the corresponding IP addresses. Application/Improvement: It is used as a space pen, security purpose for creating the digital signatures in space.Keywords
Acceleration, Handheld, Space pen, Threshold, Vectors.- Performance Analysis of Pilot Based Channel Estimation Techniques in MB OFDM Systems
Authors
1 Centre for Advanced Research, Department of Electronics and Communication Engineering, Muthayammal Engineering College, IN
Source
ICTACT Journal on Communication Technology, Vol 2, No 4 (2011), Pagination: 438-443Abstract
Ultra wideband (UWB) communication is mainly used for short range of communication in wireless personal area networks. Orthogonal Frequency Division Multiplexing (OFDM) is being used as a key physical layer technology for Fourth Generation (4G) wireless communication. OFDM based communication gives high spectral efficiency and mitigates Inter-symbol Interference (ISI) in a wireless medium. In this paper the IEEE 802.15.3a based Multiband OFDM (MB OFDM) system is considered. The pilot based channel estimation techniques are considered to analyze the performance of MB OFDM systems over Liner Time Invariant (LTI) Channel models. In this paper, pilot based Least Square (LS) and Least Minimum Mean Square Error (LMMSE) channel estimation technique has been considered for UWB OFDM system. In the proposed method, the estimated Channel Impulse Responses (CIRs) are filtered in the time domain for the consideration of the channel delay spread. Also the performance of proposed system has been analyzed for different modulation techniques for various pilot density patterns.Keywords
UWB, OFDM, Least Square, Wireless Channel, Least Minimum Mean Square.- Performance Analysis of Adiabatic Techniques using Full Adder for Efficient Power Dissipation
Authors
1 Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, IN
Source
ICTACT Journal on Microelectronics, Vol 4, No 1 (2018), Pagination: 510-514Abstract
Adiabatic circuits are low power circuits, which deals with reversible logic that it stores the power and gives it back again. Currently Several Adiabatic techniques have been adopted for efficient power dissipation. The technique used to minimize power dissipation are Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, and Pass Transistor Logic. The Adiabatic technique is mainly used for reducing the power dissipation in VLSI circuits which performs charging and discharging process. The full adder plays an important role in many arithmetic operations such as the adder, multiplier and divider and processors. In order to limit the power dissipation, an efficient full adder is designed for the different adiabatic techniques and all the circuits have been simulated by 125nm technology using tanner EDA tool.Keywords
Adiabatic Logic, Low Power Dissipation, Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, Pass Transistor Logic, Low Power Adder.References
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- Baljinder Kaur, Narinder Sharma and Gurpreet Kaur, “An Efficient Adiabatic Full Adder Design Approach for Low Power”, International Journal of Advance Research in Science and Engineering, Vol. 5, No. 5, pp. 33-41, 2016.
- Ravneet Kaur and Ashwani Kumar, “Design and Analysis of Comparator using Adiabatic ECRL and PFAL Techniques”, International Journal of Advanced Computer Technology, Vol. 4, No. 6, pp. 29-33, 2015.
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- S. Amalin Marina, T. Shunbaga Pradeepa and A. Rajeswari ‘‘Analysis of Full Adder using Adiabatic Charge Recovery Logic”, Proceedings of International Conference on Circuit, Power and Computing Technologies, pp. 73-82, 2016.
- B. Dilli Kumar and M. Barathi, “Design of Energy Efficient Arithmetic Circuits using Charge Recovery Adiabatic Logic”, International Journal of Engineering Trends and Technology, Vol. 4, No. 2, pp. 32-40, 2013.
- D. Jayanthi, A. Bhavani Shankar, S. Raghavan and G. Rajasekar, “High Speed Multi Output Circuits using Adiabatic Logic”, Proceedings of International Conference on Emerging Trends in Engineering, Technology and Science, pp. 788-798, 2016.
- Akansha Maheshwari and Surbhit Luthra, ‘‘Low Power Full Adder Circuit Implementation using Transmission Gate”, International Journal of Advanced Research in Computer and Communication Engineering, Vol. 4, No. 7, pp. 229-235, 2015.
- Nikunj R Patel and Sarman K. Hadia, “Adiabatic Logic for Low Power Application using Design in 180nm Technology”, International Journal of Computer Trends and Technology, Vol. 4, No. 4, pp. 125-138, 2013.
- Patan Yeesan Ahammad Khan and S. Rambabu, “Design of Efficient Full Adder for Low Power Applications”, International Journal and Magazine of Engineering, Technology, Management and Research, Vol. 4, No. 7,pp. 406-410, 2017.
- Yesvanthukumar and V. Sushil Kirubakaran, “Design and Analysis of Full Adder using Different Logic Techniques”, SSRG International Journal of VLSI and Signal Processing, Vol. 3, No. 5, pp. 29-34, 2016.
- Arjun Mishra and Neha Singh, “Low Power Circuit Design using Positive Feedback Adiabatic Logic (PFAL)”, International Journal of Science and Research, Vol. 3, No. 6, pp. 1-8, 2014.
- Anu Priya and Amrita Rai, “Adiabatic Technique for Power Efficient logic Circuit Design”, International Journal of Electronics and Communication Technology, Vol. 5, No. 1, pp. 70-78, 2014.
- Bhakti Patel and Poonam Kadam, “Modified PFAL Adiabatic Technique for Low Power”, Communication on Applied Electronics, Vol. 3, No. 7, pp. 40-43, 2015.
- Deepti Shinghal, Amit Saxena and Arti Noor, “Adiabatic Logic Circuits: A Retrospect”, International Journal of Electronics and Communication Engineering, Vol. 3, No. 2, pp. 108-114, 2013.
- Priyanka Ojha and Charu Rana, “Design of Low power Sequential Circuit by using Adiabatic Techniques”, International Journal of Intelligent Systems and Applications, Vol. 8, No. 5, pp. 45-50, 2015.
- Rakesh Kumar Yadav, Ashwani K. Rana and Shweta Chauhan, “Adiabatic Technique for Energy Efficient Logic Circuits Design”, Proceedings of IEEE International Conference on Emerging Trends in Electrical and Computer Technology, pp. 776-780, 2011.
- Nidhi Tiwari and Ruchi Sharma, “Implementation of Area and Energy Efficient Full Adder Cell”, Proceedings of IEEE International Conference on Recent Advances and Innovations in Engineering, pp. 661-668, 2014.
- C.H. Sansar and A. Sankhyan, “Comparative Study of Different Types of Full Adder”, International Journal of Engineering Research and Applications, Vol. 3, No. 5, pp. 1062-1064, 2013.
- C.H. Praveen Kumar, S.K. Tripathy and Rajeev Tripathi, “High Performance Sequential Circuits with Adiabatic Complementary Pass-Transistor Logic”, Proceedings of IEEE International Conference on Emerging Technologies for Sustainable Development, pp. 1-4, 2010.
- Abhishek Agal Pardeep and Bal Krishan, “comparative Analysis of Various SRAM Cells with Low Power, High Read Stability and Low Area”, Indian Journal of Endocrinology and Metabolism, Vol. 4, No. 3, pp. 1-12, 2014.
- Yangbo Wu, Jindan Chem and Jianping Hu, “Near-Threshold Computing of ECRL Circuits for Ultra-Low Power Application”, Springer, 2011.
- Neha Arora, B.P. Singh, Tripti Sharma and K.G. Sharma, “Adiabatic and Standard CMOS Interfaces at 90nm Technology”, WSEAS Transactions on Circuits and Systems, Vol. 9, No. 3, pp. 173-183, 2010.
- A Smart Billing System using Arduino Mega and RFID
Authors
1 Department of Electronics and Communication Engineering, Sri Eshwar College of Engineering, Coimbatore, TamilNadu, IN
Source
Digital Signal Processing, Vol 11, No 3 (2019), Pagination: 45-47Abstract
In the developing technology we are seeing many inventions in various fields including automatic machines, Internet Of Things and so on. There is a drastic increase of expectations in customer’s point of view. With the developing world, people always find the easy way to satisfy their needs and to use their time appropriately. In day-to-day life purchasing various products in malls or supermarkets require a trolley. Product procurement is a complex process. Each time customer has to push the trolley from rack to rack for collecting products and simultaneously customers are wasting their precious time and not willing to stand in long queue in order for the billing process. Our project is to scan the products by their own efforts which are going to be purchased. Each time product is added into trolley and cost of the each product is also calculated and displayed on the LCD. Mainly to find the location of the product Bluetooth mobile connectivity can be used. At the end, customer has to wait in queue for billing and payment. To overcome that we have developed a smart way for shopping. In this paper, we are presenting a smart shopping system using RFID and ARDUINO MEGA controller.
Keywords
RFID, Module, Arduinomega, Bluetooth, Smart Shopping.References
- Mr.P. Chandrasekar and Ms.T. Sangeetha”Smart Shopping Cart with Automatic Billing System through RFID and ZigBee”, IEEE, 2014.
- Ms.Vrinda, Niharika, “Novel Model for Automating Purchases using Intelligent Cart,” e-ISSN: 2278-0661, p- ISSN: 2278-8727Volume16, Issue 1, Ver. VII (Feb. 2014), PP 23-30.
- Ms.RupaliSawant, Kripa Krishnan, ShwetaBhokre, PriyankaBhosale “The RFID Based Smart Shopping Cart”, International Journalof Engineering Research and General Science Volume 3, Issue 2 pp 275-280, March-April, 2015.
- KalyaniDawkhar, ShraddhaDhomase, Samruddhi Mahabaleshwarkar “Electronic Shopping Cart for Effective Shopping based on RFID”, International Journal of Innovative Research In Electrical, Electronic, Instrumentation And Control Engineering Vol. 3, Issue 1 pp 84-86, January 2015.
- Zeeshan Ali, ReenaSonkusare, “RFID Based Smart Shopping and Billing ", International Journal of Advanced Research in Computer and Communication Engineering, Vol. 2, Issue 12, December 2013
- Raju Kumar, K. Gopalakrishna, K. Ramesha, “Intelligent Shopping Cart,” International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 4, July 2013.
- EktaMaini and JyotiShettar” Wireless Intelligent Billing Trolley for Malls, International Journal of Scientific Engineering and Technology Volume No.3 Issue No.9, pp: 1175-1178.
- SatishKamble, SachinMeshram, Rahul Thokal, RoshanGakre “Developing a Multitasking Shopping Trolley Based On RFID Technology”, International Journal of Soft Computing and Engineering (IJSCE), Volume-3, Issue-6, January 2014.
- Rahmani.E, "Zigbee/IEEE 802.15.4", University of Tehran, 2005.
- GalandeJayshree, RutujaGholap, PreetiYadav”RFID Based Automatic Billing Trolley, International Journal of Emerging Technology and Advanced Engineering Volume 4, Issue 3, March 2014.
- Ergen, S. C., “ZigBee/IEEE 802.15.4 Summary,” EECS Berkely, September.6
- Challenges and Developments in Numerical Distance Protection
Authors
1 Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai - 600036, IN